Approximate synthesis is a recent trend in logic synthesis where one changes some outputs of a logic specification, withinthe error tolerance of a given application, to reduce the complexity of the final implementation. We attack the problem by exploiting theallowed flexibility in order to maximize the regularity of the specified Boolean functions. Specifically, we consider two types of regularity:symmetryandD-reducibility, and contribute two algorithms to find, respectively, a symmetric and a D-reducible approximation of agiven target functionf, within the given error rate threshold if possible. When targeting symmetry, we characterize and computepolynomially the closest symmetric approximation, i.e., the symmetric function obtained by injecting the minimum number of errors inthe original incompletely specified Boolean function, with an unbounded number of errors; then, we discuss strategies to achievepartial symmetrization of the original specification while satisfying given error bounds. Finally, we present a polynomial heuristicalgorithm to compute a D-reducible approximation of an incompletely specified target function, under a bit error metric. Experimentalresults on classical and new benchmarks confirm the effectiveness of the proposed approaches.
Exploiting Symmetrization and D-reducibility for Approximate Logic Synthesis / A. Bernasconi, V. Ciriani, T. Villa. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - (2020), pp. 1-13. [Epub ahead of print]
Titolo: | Exploiting Symmetrization and D-reducibility for Approximate Logic Synthesis |
Autori: | CIRIANI, VALENTINA (Secondo) |
Parole Chiave: | Logic synthesis; Approximate synthesis;, Regular Boolean functions; |
Settore Scientifico Disciplinare: | Settore INF/01 - Informatica |
Data di pubblicazione: | 2020 |
Rivista: | |
Tipologia: | Article (author) |
Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/TC.2020.3043476 |
Appare nelle tipologie: | 01 - Articolo su periodico |
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