Approximate synthesis is a recent trend in logic synthesis that changes some outputs of a logic specification to take advantage of error tolerance of some applications and reduce complexity and consumption of the final implementation. We propose a new approach to approximate synthesis of combinational logic where we derive its closest symmetric approximation, i.e., the symmetric function obtained by injecting the minimum number of errors in the original function. Since BDDs of totally symmetric functions are quite compact, this approach is particularly convenient for BDD-based implementations, such as networks of MUXes directly mapped from BDDs. Our contribution is twofold: first we propose a polynomial algorithm for computing the closest symmetric approximation of an incompletely specified Boolean function with an unbounded number of errors; then we discuss strategies to achieve partial symmetrization of the original specification while satisfying given error bounds. Experimental results on classical and new benchmarks confirm the efficacy of the proposed approach.
Approximate Logic Synthesis by Symmetrization / A. Bernasconi, V. Ciriani, T. Villa (PROCEEDINGS DESIGN, AUTOMATION, AND TEST IN EUROPE CONFERENCE AND EXHIBITION). - In: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)[s.l] : IEEE, 2019. - ISBN 9783981926323. - pp. 1655-1660 (( convegno Design, Automation & Test in Europe (DATE) tenutosi a Firenze nel 2019.
|Titolo:||Approximate Logic Synthesis by Symmetrization|
|Settore Scientifico Disciplinare:||Settore INF/01 - Informatica|
|Data di pubblicazione:||2019|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.23919/DATE.2019.8715286|
|Tipologia:||Book Part (author)|
|Appare nelle tipologie:||03 - Contributo in volume|