Synthesis of integer multipliers in sum of pseudoproducts form

We discuss the realization of two standard multiplier structures in a three-level form based on EXOR, called sum of pseudoproducts (SPP for short). SPP extends the classical two-level sum of products form (SOP). Our study focuses on the minimization of the number of gates and levels of the circuits needed to construct Wallace-type multipliers, and a 54 × 54-bit multiplier. The basic building blocks explicitly studied are the 4 × 4 parallel multiply module, and the family of carry-save adders Ci, with i input lines, that compose the Wallace trees. We show that the ratio of the number of gates of Ci in SPP over SOP decreases exponentially with i, being very small even for small values of i (ratio > 0.2 for i = 9). The evaluation of power, speed, and chip area with three different standard tools also shows the interest of the proposed approach.