Switching lattices are two-dimensional arrays of four-terminal switches proposed in a seminal paper by Akers in 1972 to implement Boolean functions. Recently, with the advent of a variety of emerging nanoscale technologies based on regular arrays of switches, synthesis methods targeting lattices of multi-terminal switches have found a renewed interest. In this paper, the testability under the stuck-at-fault model (SAFM) of switching lattices is analyzed, and properties of fully testable lattices are identified and discussed. Experimental results are given to analyze the testability of lattices synthesized with different methods.
Testability of Switching Lattices in the Stuck at Fault Model / A. Bernasconi, V. Ciriani, L. Frontini - In: 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)[s.l] : IEEE, 2019. - ISBN 9781538647561. - pp. 213-218 (( Intervento presentato al 26. convegno IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC tenutosi a Verona nel 2018 [10.1109/VLSI-SoC.2018.8644806].
Testability of Switching Lattices in the Stuck at Fault Model
V. Ciriani;L. Frontini
2019
Abstract
Switching lattices are two-dimensional arrays of four-terminal switches proposed in a seminal paper by Akers in 1972 to implement Boolean functions. Recently, with the advent of a variety of emerging nanoscale technologies based on regular arrays of switches, synthesis methods targeting lattices of multi-terminal switches have found a renewed interest. In this paper, the testability under the stuck-at-fault model (SAFM) of switching lattices is analyzed, and properties of fully testable lattices are identified and discussed. Experimental results are given to analyze the testability of lattices synthesized with different methods.File | Dimensione | Formato | |
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