8 PDB pre‐production boards (version 3) received in Milano end of February Differences between version 3 and previous version (version 2): 1. Different values of some resistors in order to optimize a few output voltages as requested by Hao after some tests of PDB v2 in the LTDB 2. Some geometrical changes implemented in the frame Of the 8 pre‐production PDBS: • 4 boards were not useable because of a mistake made by the manufacturer (problem understood – see March Lar week presentation https://indico.cern.ch/event/800559/contributions/3339352/attachments/1806520/2948521/PDB‐LTM_2019‐03‐05.pdf ) • 4 boards were successfully tested in Milano and 3 of them were sent to BNL During the tests in BNL, a start up sequence not correct in some situation was observed. The problem could not be reproduced in Milano with the other v3 board. Moreover the problem was not observed with v2 boards (neither in Milano nor in BNL) Investigation on this issue started and the problem was traced to dependencies on the LVPS used in the tests. Milano had used always the same LVPS in the tests, BNL used not only the Wiener LVPS but also other devices (Vicor and Keysight). Moreover the input capacitors of the LTDB were changed to be compatible with 48 V input voltage for Phase II: – to be compatible with the footprint in the LTDB layout the capacitance was slightly reduced.
PDB issues and Production Plan / M. Citterio, M. Lazzaroni, S. Latorre, F. Tartarelli. ((Intervento presentato al convegno AUW tenutosi a mm nel 2019.
PDB issues and Production Plan
M. Citterio;M. Lazzaroni
;F. Tartarelli
2019
Abstract
8 PDB pre‐production boards (version 3) received in Milano end of February Differences between version 3 and previous version (version 2): 1. Different values of some resistors in order to optimize a few output voltages as requested by Hao after some tests of PDB v2 in the LTDB 2. Some geometrical changes implemented in the frame Of the 8 pre‐production PDBS: • 4 boards were not useable because of a mistake made by the manufacturer (problem understood – see March Lar week presentation https://indico.cern.ch/event/800559/contributions/3339352/attachments/1806520/2948521/PDB‐LTM_2019‐03‐05.pdf ) • 4 boards were successfully tested in Milano and 3 of them were sent to BNL During the tests in BNL, a start up sequence not correct in some situation was observed. The problem could not be reproduced in Milano with the other v3 board. Moreover the problem was not observed with v2 boards (neither in Milano nor in BNL) Investigation on this issue started and the problem was traced to dependencies on the LVPS used in the tests. Milano had used always the same LVPS in the tests, BNL used not only the Wiener LVPS but also other devices (Vicor and Keysight). Moreover the input capacitors of the LTDB were changed to be compatible with 48 V input voltage for Phase II: – to be compatible with the footprint in the LTDB layout the capacitance was slightly reduced.File | Dimensione | Formato | |
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PDB-LTM_2019-04-08 Final.pdf
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