Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.

Integrated Synthesis Methodology for Crossbar Arrays / M.C. Morgul, D. Alexandrescu, O. Tunali, M. Altun, L. Frontini, V. Ciriani, E.I. Vatajelu, L. Anghel, C.A. Moritz, M.R. Stan, D. Alexandrescu - In: NANOARCH '18 : Proceedings[s.l] : ACM, 2018. - ISBN 9781450358156. - pp. 91-97 (( Intervento presentato al 14. convegno IEEE/ACM International Symposium on Nanoscale Architectures tenutosi a Athens nel 2018 [10.1145/3232195.3232211].

Integrated Synthesis Methodology for Crossbar Arrays

L. Frontini;V. Ciriani
;
2018

Abstract

Nano-crossbar arrays have emerged as area and power efficient structures with an aim of achieving high performance computing beyond the limits of current CMOS. Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.
Crossbar Arrays; Logic Synthesis; Defect Tolerance; Fault Tolerance; Performance Optimization; Memristor Arrays
Settore INF/01 - Informatica
2018
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2434/619212
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