The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.
Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC / R.J. Aliaga, V. Herrero Bosch, S. Capra, A. Pullia, J.A. Dueñas, L. Grassi, A. Triossi, C. Domingo Pardo, R. Gadea, V. González, T. Hüyük, E. Sanchís, A. Gadea, D. Mengoni. - In: NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH. SECTION A, ACCELERATORS, SPECTROMETERS, DETECTORS AND ASSOCIATED EQUIPMENT. - ISSN 0168-9002. - 800(2015 Nov 11), pp. 34-39. [10.1016/j.nima.2015.07.067]
Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC
S. Capra;A. Pullia;
2015
Abstract
The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.File | Dimensione | Formato | |
---|---|---|---|
Conceptual design of the TRACE detector readout using a compact dead time-less analog memory ASIC.pdf
accesso aperto
Tipologia:
Post-print, accepted manuscript ecc. (versione accettata dall'editore)
Dimensione
498.71 kB
Formato
Adobe PDF
|
498.71 kB | Adobe PDF | Visualizza/Apri |
Conceptual design of the TRACE detector readout using a compact dead time-less analog memory ASIC.pdf
accesso riservato
Tipologia:
Publisher's version/PDF
Dimensione
583.85 kB
Formato
Adobe PDF
|
583.85 kB | Adobe PDF | Visualizza/Apri Richiedi una copia |
Paper 2015 NIMA (preprint).pdf
accesso aperto
Tipologia:
Pre-print (manoscritto inviato all'editore)
Dimensione
413.76 kB
Formato
Adobe PDF
|
413.76 kB | Adobe PDF | Visualizza/Apri |
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.