The paper presents the design of an integrated circuit (IC) for a 10MHz low power-loss driver for GaN HFETs. While the main elements of the topology were introduced in a previous work, here the authors focus on the design of the IC and present preliminary results and considerations. The driver circuit proposed, based upon new two-stage positive-to-negative level shifters and resonant topology, has been designed and implemented using the cost-effective Smart Voltage extension (SVX) technique. Detailed analysis of the design process as well as a full set of simulations, reported in the paper, fully demonstrate the possibility to exploit the advantages of GaN devices by means of a smart and convenient implementation.
|Titolo:||Integrated circuit implementation for a GaN HFETs driver circuit|
|Autori interni:||RIVA, MARCO (Secondo)|
|Settore Scientifico Disciplinare:||Settore ING-INF/01 - Elettronica|
|Data di pubblicazione:||feb-2008|
|Digital Object Identifier (DOI):||10.1109/APEC.2008.4522828|
|Tipologia:||Book Part (author)|
|Appare nelle tipologie:||03 - Contributo in volume|