The paper presents the design of an integrated circuit (IC) for a 10MHz low power-loss driver for GaN HFETs. While the main elements of the topology were introduced in a previous work, here the authors focus on the design of the IC and present preliminary results and considerations. The driver circuit proposed, based upon new two-stage positive-to-negative level shifters and resonant topology, has been designed and implemented using the cost-effective Smart Voltage extension (SVX) technique. Detailed analysis of the design process as well as a full set of simulations, reported in the paper, fully demonstrate the possibility to exploit the advantages of GaN devices by means of a smart and convenient implementation.
Integrated circuit implementation for a GaN HFETs driver circuit / B. Wang, M. Riva, J. Bakos, A. Monti - In: APEC 2008 : 23. IEEE applied power electronics conference and expositionPiscataway, N.J. : IEEE, 2008 Feb. - ISBN 978-1-4244-1873-2. - pp. 901-906 (( Intervento presentato al 23. convegno Annual IEEE Applied Power Electronics Conference and Exibition tenutosi a Austin, Texas nel 2008.
Integrated circuit implementation for a GaN HFETs driver circuit
M. RivaSecondo
;
2008
Abstract
The paper presents the design of an integrated circuit (IC) for a 10MHz low power-loss driver for GaN HFETs. While the main elements of the topology were introduced in a previous work, here the authors focus on the design of the IC and present preliminary results and considerations. The driver circuit proposed, based upon new two-stage positive-to-negative level shifters and resonant topology, has been designed and implemented using the cost-effective Smart Voltage extension (SVX) technique. Detailed analysis of the design process as well as a full set of simulations, reported in the paper, fully demonstrate the possibility to exploit the advantages of GaN devices by means of a smart and convenient implementation.Pubblicazioni consigliate
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