During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small while circuits with low depth are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose a synthesis technique that allows to trade-off between area and delay. Moreover, the resulting circuits are 100105 testable under the stuck-at fault model. The proposed approach relies on the combination of 100% testable circuits derived from binary decision diagrams and 2-SPP networks. Full testability under the stuck-at fault model is proven and experimental results show the trade-off between area and depth.

On the construction of small fully testable circuits with low depth / G. Fey, A. Bernasconi, V. Ciriani, R. Drechsler - In: Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on / [a cura di] H. Kubátová. - Los Alamitos : IEEE, 2007. - ISBN 076952978X. - pp. 563-569 (( Intervento presentato al 10. convegno Euromicro Conference on Digital System Design tenutosi a Lübeck nel 2007.

On the construction of small fully testable circuits with low depth

V. Ciriani
Penultimo
;
2007

Abstract

During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small while circuits with low depth are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose a synthesis technique that allows to trade-off between area and delay. Moreover, the resulting circuits are 100105 testable under the stuck-at fault model. The proposed approach relies on the combination of 100% testable circuits derived from binary decision diagrams and 2-SPP networks. Full testability under the stuck-at fault model is proven and experimental results show the trade-off between area and depth.
Settore INF/01 - Informatica
EUROMICRO
Book Part (author)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2434/37682
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