Recently introduced, three-level logic Sum of Pseudoproducts (SPP) forms allow the representation of Boolean functions with much shorter expressions than standard two-level Sum of Products (SOP) forms, or other three-level logic forms. In this paper the testability of circuits derived from SPPs is analyzed. We study testability under the Stuck-At Fault Model (SAFM). For SPP networks several minimal forms can be considered. While full testability can be proved for some classes, others are shown to contain redundancies. Experimental results are given to demonstrate the efficiency of the approach.
Stuck-at-fault testability of SPP three-level logic forms / V. Ciriani, A. Bernasconi, R. Drechsler - In: VLSI-SOC: From Systems to Chips / [a cura di] M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking. - New York : Springer, 2006. - ISBN 0387334025. - pp. 299-313 (( Intervento presentato al 12. convegno International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003) tenutosi a Darmstadt nel 2003.
Stuck-at-fault testability of SPP three-level logic forms
V. Ciriani;
2006
Abstract
Recently introduced, three-level logic Sum of Pseudoproducts (SPP) forms allow the representation of Boolean functions with much shorter expressions than standard two-level Sum of Products (SOP) forms, or other three-level logic forms. In this paper the testability of circuits derived from SPPs is analyzed. We study testability under the Stuck-At Fault Model (SAFM). For SPP networks several minimal forms can be considered. While full testability can be proved for some classes, others are shown to contain redundancies. Experimental results are given to demonstrate the efficiency of the approach.
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
