2-SPP approximate synthesis for error tolerant applications

We propose an approximate logic synthesis heuristic for synthesizing a 2-SPP circuit under a given error rate threshold. 2-SPP circuits are three-level EXOR-AND-OR forms with EXOR gates restricted to fan-in 2. They represent a direct generalization of SOP forms, obtained generalizing cubes to "2-pseudocubes" where literals in cubes may be replaced by 2-EXOR factors in 2-pseudocubes. We discuss and experimentally evaluate two different measures for the error: the bit threshold and the minterm threshold. The first metric considers the overall number of complemented output bits, while the second metric is related to the number of input vectors on which the output computed by the circuit is different from the exact one on at least one bit. Experimental results confirm the effectiveness of the proposed approach. For an error rate threshold of 1%, our heuristic for approximate 2-SPP synthesis provides an average reduction of the number of 2-pseudocubes in the cover of about 23% for all the considered benchmarks, when we consider the bit threshold error metric. The reduction in the number of 2-pseudocubes is interesting even in the minterm threshold error metric, especially when we perform the resynthesis of the derived approximate versions of the benchmarks: the average gain, without resynthesis is of about 8%, while the average gain with resynthesis becomes 15%.