We propose a new synthesis approach based on the SPP three-level logic minimization of D-reducible Boolean functions. This approach supplies a new tool for efficient minimization, based on the idea of exploiting a Boolean function regularity to get more compact expressions. D-reducible functions can be efficiently synthesized giving rise to new four-level logic forms called DRedSPP. These forms are often smaller than the corresponding minimum SPP forms, and are fully testable under the Stuck-At Fault Model. Moreover, the computational time needed to derive a DRedSPP form for a D-reducible function f is nearly always less than the time required to derive an SPP representation of f.

Compact and testable circuits for regular functions / A. Bernasconi, V. Ciriani - In: Architecture of computing systemsBerlin : VDE, 2011. - ISBN 9783800733330. - pp. 193-202 (( Intervento presentato al 24. convegno Architecture of computing systems (ARCS) tenutosi a Como nel 2011.

Compact and testable circuits for regular functions

V. Ciriani
Ultimo
2011

Abstract

We propose a new synthesis approach based on the SPP three-level logic minimization of D-reducible Boolean functions. This approach supplies a new tool for efficient minimization, based on the idea of exploiting a Boolean function regularity to get more compact expressions. D-reducible functions can be efficiently synthesized giving rise to new four-level logic forms called DRedSPP. These forms are often smaller than the corresponding minimum SPP forms, and are fully testable under the Stuck-At Fault Model. Moreover, the computational time needed to derive a DRedSPP form for a D-reducible function f is nearly always less than the time required to derive an SPP representation of f.
Settore INF/01 - Informatica
2011
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2434/158947
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