In logic synthesis, the “regularity” of a Boolean function can be exploited with the purpose of decreasing the cost of the corresponding algebraic expression or its minimization time. In this paper we study the synthesis of a class of regular Boolean functions called D-reducible. We propose two compact and testable representations of D-reducible non completely specified functions, called DRedSOP and 2DRedSOP. The experimental results show that a large percentage (about 70%) of the benchmark functions have at least a D-reducible output. The gain in area of the synthesized networks for such functions is, on average, 27% for DRedSOPs and 28% for 2DRedSOPs.
Logic synthesis and testability of D-reducible functions / A. Bernasconi, V. Ciriani - In: Proceedings of the 2010 18. IEEE/IFIP international conference on VLSI and system-on-chip : 27–29 september 2010 : Computer Science School, Complutense University of MadridPiscataway : Institute of electrical and electronics engineers, 2010. - ISBN 9781424464692. - pp. 280-285 (( Intervento presentato al 18. convegno IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC) tenutosi a Madrid nel 2010.
Logic synthesis and testability of D-reducible functions
V. CirianiUltimo
2010
Abstract
In logic synthesis, the “regularity” of a Boolean function can be exploited with the purpose of decreasing the cost of the corresponding algebraic expression or its minimization time. In this paper we study the synthesis of a class of regular Boolean functions called D-reducible. We propose two compact and testable representations of D-reducible non completely specified functions, called DRedSOP and 2DRedSOP. The experimental results show that a large percentage (about 70%) of the benchmark functions have at least a D-reducible output. The gain in area of the synthesized networks for such functions is, on average, 27% for DRedSOPs and 28% for 2DRedSOPs.
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