Polynomial Formal Verification (PFV) ensures that a class of circuits can be verified efficiently by calculating polynomial upper bounds for the resource demands of the verification process. In this paper, we address the PFV of Boolean affine spaces represented by a 2-XOR sum of products. We show that time and space resources remain quadratic in the number of input variables during the entire verification process. Specifically, we prove that the dimensions of ROBDDs and QRBDDs representing a 2-affine space are linear. Furthermore, we prove that all ROBDDs generated during the symbolic simulation of the circuit can be computed in linear time. Finally, we provide an overall quadratic upper bound for the formal verification of QRBDD-based circuits. The experimental results confirm the given bounds.

Polynomial Verification of 2-Affine Spaces / A. Bernasconi, V.C. (PROCEEDINGS DESIGN, AUTOMATION, AND TEST IN EUROPE CONFERENCE AND EXHIBITION). - In: DATE Design, Automation and Test in Europe Conference and Exhibition[s.l] : Institute of Electrical and Electronics Engineers (IEEE), 2026. - ISBN 978-3-9826741-1-7. - pp. 1-7 (( The European Event for Electronic System Design & Test : April, 20 – 22 Verona 2026 [10.23919/date69613.2026.11539079].

Polynomial Verification of 2-Affine Spaces

V. Ciriani
Secondo
;
G. Cuciniello;
2026

Abstract

Polynomial Formal Verification (PFV) ensures that a class of circuits can be verified efficiently by calculating polynomial upper bounds for the resource demands of the verification process. In this paper, we address the PFV of Boolean affine spaces represented by a 2-XOR sum of products. We show that time and space resources remain quadratic in the number of input variables during the entire verification process. Specifically, we prove that the dimensions of ROBDDs and QRBDDs representing a 2-affine space are linear. Furthermore, we prove that all ROBDDs generated during the symbolic simulation of the circuit can be computed in linear time. Finally, we provide an overall quadratic upper bound for the formal verification of QRBDD-based circuits. The experimental results confirm the given bounds.
Settore INFO-01/A - Informatica
2026
ACM Special Interest Group on Design Automation (SIGDA)
Cadence
Institute of Electrical and Electronics Engineers (IEEE)
European Design and Automation Association (EDA)
Council on Electronic Design Automation (CEDA)
Semi | Electronic System Design (ESD) Alliance
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2434/1258015
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