We propose a CMOS architecture for spiking neural networks with permanent memory and online learning. It uses a three-transistors synapse with a floating node that stores the synaptic weight, programmed by using only Fowler-Nordheim tunneling current in the pA range for ultra-low power operation. A neuron with a conditioning circuit programs the floating gate synapse following the spike timing dependent plasticity rule. Simulations using a standard 150 nm CMOS process show the online learning capabilities of the architecture.
Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity / M. Mastella, F. Toso, G. Sciortino, E. Prati, G. Ferrari - In: 2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)[s.l] : IEEE, 2020. - ISBN 978-1-7281-4922-6. - pp. 213-217 (( convegno IEEE International Conference on Artificial Intelligence Circuits and Systems tenutosi a Genova nel 2020 [10.1109/aicas48895.2020.9073965].
Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity
E. Prati;
2020
Abstract
We propose a CMOS architecture for spiking neural networks with permanent memory and online learning. It uses a three-transistors synapse with a floating node that stores the synaptic weight, programmed by using only Fowler-Nordheim tunneling current in the pA range for ultra-low power operation. A neuron with a conditioning circuit programs the floating gate synapse following the spike timing dependent plasticity rule. Simulations using a standard 150 nm CMOS process show the online learning capabilities of the architecture.
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
