From the quantum Moore's law toward silicon based universal quantum computing

Forthcoming CMOS technology nodes are in principle sufficient for achieving both the quantum information density and the speed that are critical for error-free logical qubits. Using data from the roadmap for semiconductor devices from ITRS and IEDM, we applied the standard CMOS design rules to a universal set of quantum logic gates to control silicon qubits. We consequently obtain a scaling law for quantum information density for Steane code, concatenated codes, and surface code, which represent the quantum information equivalent of Moore's law in terms of density scaling per node. By imposing the constraints due to both quantum error correction and the intrinsic operation speed limitation of a physical silicon qubit, we determine that technology nodes below 14 nm can in principle support error-free logical qubits manipulated at GHz frequency. We review the current state-of-the-art of silicon technology to assess the performance of different silicon qubit architectures based on CMOS single donors and double quantum dot devices. Our analysis demonstrates that silicon technology is compatible with the scalability requirements imposed by quantum error correction architectures for universal quantum computing. Such considerations provide a benchmark for the development of a silicon-based quantum computer and a general guideline for other quantum technology platforms.