SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

The SALT—readout ASIC for silicon strip sensors of upstream tracker in the upgraded LHCb experiment / C.A. Beteta, D. Andreou, M. Artuso, A. Beiter, S. Blusk, R. Bugiel, S. Bugiel, A. Carbone, I. Carli, B. Chen, N. Conti, F. De Benedetti, S. Ding, S. Ely, M. Firlej, T. Fiutowski, P. Gandini, D. Germann, N. Grieser, M. Idzik, X. Jiang, W. Krupa, Y. Li, Z. Li, X. Liang, S. Liu, Y. Lu, L. Mackey, J. Moron, R. Mountain, M. Petruzzo, H. Pham, B. Schmidt, S. Sheng, E.S. Norella, K. Swientek, T. Szumlak, M. Tobin, J. Wang, M. Wilkinson, H. Wu, F. Zhang, Q. Zou. - In: SENSORS. - ISSN 1424-8220. - 22:1(2022 Jan), pp. 107.1-107.21. [10.3390/s22010107]

The SALT—readout ASIC for silicon strip sensors of upstream tracker in the upgraded LHCb experiment

A. Carbone;M. Petruzzo;
2022-01

Abstract

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.
ADC; ASIC; DLL; DSP; Front-end; PLL; SEE
Settore FIS/01 - Fisica Sperimentale
H2020_ERC18NNERI_01 - Search for the electric dipole moment of strange and charm baryons at LHC - SELDOM - NERI, NICOLA - H2020_ERC - Horizon 2020_Europern Research Council - 2018
24-dic-2021
https://www.mdpi.com/1424-8220/22/1/107
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/2434/905885
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