This article describes a design of an field-programmable gate array (FPGA) implementation of a clock and data recovery (CDR) system. The core will be integrated in the FPGA configuration for the front-end electronics (FEE) board of the Jiangmen underground neutrino observatory (JUNO) experiment. The front-end will be placed on the main detector, underground and underwater, making the electronics not accessible after installation. The timing and trigger system relies on a synchronous link connection over CAT5e cable (up to 100 m long) between the front-end and the back-end electronics (BEE), where a twisted-pair is dedicated to clock-forwarding. The robustness of the recovery clock system is essential for the stability of the FPGA firmware. The proposed project is intended to improve the clock recovery operation by increasing the immunity of the link to sudden electromagnetic interference (EMI). On top of this, the core allows to free a twisted-pair in the link, since the clock can be recovered from the data and there is no more need for a clock-dedicated transmission. This will optimize the link granting the possibility to implement other features. The design is based on two components: a numerically-controlled oscillator (NCO), in order to create a controlled frequency clock signal, and a digital phase detector (PD) to match the clock frequency with the data rate. NCOs are often coupled with a digital-to-analog converter (DAC) to create direct digital synthesizers (DDSs), which are able to produce analog waveforms of any desired frequency. In the presented case instead, the NCO generates a digital clock signal of an arbitrary frequency, while the PD manages this frequency by intercepting any shifting on the relative phase between the clock and the data. A phase aligner (PA) module guarantees that data are sampled in the middle of the eye pattern, which represents the optimal sampling point. The article presents an overview of the NCO-based CDR design and implementation, together with some tests and results in order to verify the CDR reliability. Moreover, in the last section, some other possible applications of the core are illustrated.

FPGA Implementation of an NCO Based CDR for the JUNO Front-End Electronics / F. Marini, M. Bellato, A. Bergnoli, R. Brugnera, F. Dal Corso, D. Corti, J. Dong, A. Garfagnini, A. Giaz, G. Gong, J. Hu, R. Isocrate, X. Jiang, I. Lippi, K. Von Sturm, S. Aiello, G. Andronico, V. Antonelli, W. Bandini, D. Basilico, A. Brigatti, A. Barresi, A. Budano, R. Bruno, B. Caccianiga, A. Cammi, R. Caruso, D. Chiesa, C. Clementi, S. Costa, X. Ding, S. Dusini, A. Fabbri, M. Fargetta, R. Ford, A. Formozov, M. Giammarchi, M. Grassi, C. Landini, P. Lombardi, C. Lombardo, F. Mantovani, S.M. Mari, C. Martellini, A. Martini, E. Meroni, M. Mezzetto, L. Miramonti, P. Montini, M. Montuschi, M. Nastasi, F. Ortica, A. Paoloni, S. Parmeggiano, N. Pelliccia, E. Previtali, G. Ranucci, D. Riondino, A.C. Re, B. Ricci, A. Romani, P. Saggese, A. Serafini, C. Sirignano, M. Sisti, L. Stanco, V. Strati, M. Torri, C. Tuve, G. Verde, L. Votano. - In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE. - ISSN 0018-9499. - 68:8(2021), pp. 9442732.1952-9442732.1960. [10.1109/TNS.2021.3084446]

FPGA Implementation of an NCO Based CDR for the JUNO Front-End Electronics

V. Antonelli;D. Basilico;B. Caccianiga;L. Miramonti;A.C. Re;M. Torri;
2021

Abstract

This article describes a design of an field-programmable gate array (FPGA) implementation of a clock and data recovery (CDR) system. The core will be integrated in the FPGA configuration for the front-end electronics (FEE) board of the Jiangmen underground neutrino observatory (JUNO) experiment. The front-end will be placed on the main detector, underground and underwater, making the electronics not accessible after installation. The timing and trigger system relies on a synchronous link connection over CAT5e cable (up to 100 m long) between the front-end and the back-end electronics (BEE), where a twisted-pair is dedicated to clock-forwarding. The robustness of the recovery clock system is essential for the stability of the FPGA firmware. The proposed project is intended to improve the clock recovery operation by increasing the immunity of the link to sudden electromagnetic interference (EMI). On top of this, the core allows to free a twisted-pair in the link, since the clock can be recovered from the data and there is no more need for a clock-dedicated transmission. This will optimize the link granting the possibility to implement other features. The design is based on two components: a numerically-controlled oscillator (NCO), in order to create a controlled frequency clock signal, and a digital phase detector (PD) to match the clock frequency with the data rate. NCOs are often coupled with a digital-to-analog converter (DAC) to create direct digital synthesizers (DDSs), which are able to produce analog waveforms of any desired frequency. In the presented case instead, the NCO generates a digital clock signal of an arbitrary frequency, while the PD manages this frequency by intercepting any shifting on the relative phase between the clock and the data. A phase aligner (PA) module guarantees that data are sampled in the middle of the eye pattern, which represents the optimal sampling point. The article presents an overview of the NCO-based CDR design and implementation, together with some tests and results in order to verify the CDR reliability. Moreover, in the last section, some other possible applications of the core are illustrated.
Clock and data recovery (CDR); eye pattern; field-programmable gate array (FPGA); numerically-controlled oscillator (NCO); phase detector (PD); phase aligner (PA)
Settore FIS/01 - Fisica Sperimentale
Settore FIS/04 - Fisica Nucleare e Subnucleare
Article (author)
File in questo prodotto:
File Dimensione Formato  
FPGA_Implementation_of_an_NCO_Based_CDR_for_the_JUNO_Front-End_Electronics.pdf

accesso riservato

Tipologia: Publisher's version/PDF
Dimensione 1.57 MB
Formato Adobe PDF
1.57 MB Adobe PDF   Visualizza/Apri   Richiedi una copia
Pubblicazioni consigliate

Caricamento pubblicazioni consigliate

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2434/880289
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 1
  • ???jsp.display-item.citation.isi??? 1
social impact