PLAS: A compact, self-triggered, dead time-less, high channel count analog memory ASIC for TRACE

The readout system for the new TRACE detector requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. A triggerless solution has been chosen involving front-end analog memories that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while performing zero suppression and serialization tasks. An analog memory ASIC named PLAS (for PipeLined Asymmetric SCA) is presented that allows pulse capture with no dead time in any channel while reducing die area requirements for high input channel counts. The circuit is based on a novel architecture where the typical Switched Capacitor Array (SCA) structure is partitioned into two asymmetric stages and FIFO queue-like control circuitry is introduced for captured data. The ASIC has been designed in 0.18 μm CMOS technology with 32 independent, self-triggered input channels and a size of 3.5 × 3.9mm2. Simulations predict figures around 100MHz bandwidth, 12 ENOB and 10 mW per channel.