This paper presents the design of a charge sensitive amplifier (CSA) for an analog processing circuit of 47×6 silicon pixel detector array. The design has been implemented in BCD 180 nm technology. A diode with an area of 250 × 50 µm2 is used to realize a unit sensor pixel. A 100 % fill factor is achieved by confining the analog circuit in the diode. Low power and area efficient single ended folded cascode amplifier is employed as a basic building block of the CSA. Further, an on-chip corner control circuit is proposed to make the design insensitive to process variations and to reduce power dissipation in the CSA.
Design of a charge sensitive amplifier for silicon particle detector in BCD 180 nm process / I. Yadav, A. Joshi, E. Ruscino, V. Liberali, A. Andreazza, H. Shrimali - In: 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)[s.l] : IEEE, 2019 Jan. - ISBN 9781728104096. - pp. 541-542 (( Intervento presentato al 32. convegno International Conference on VLSI Design tenutosi a Delhi nel 2019.
Titolo: | Design of a charge sensitive amplifier for silicon particle detector in BCD 180 nm process |
Autori: | |
Parole Chiave: | Active pixel sensors; image sensors; low-frequency noise; low-noise amplifiers; radiation hardening |
Settore Scientifico Disciplinare: | Settore FIS/01 - Fisica Sperimentale Settore ING-INF/01 - Elettronica |
Data di pubblicazione: | gen-2019 |
Enti collegati al convegno: | VLSI Society of India |
Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/VLSID.2019.00126 |
Tipologia: | Book Part (author) |
Appare nelle tipologie: | 03 - Contributo in volume |
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