The paper provides a design methodology for embedded classifiers particularly effective in those applications characterised by a temporal locality of the inputs. By exploiting application locality we reduce computational complexity and cache misses (hence speeding up the execution) as well as power consumption. A gated-parallel neural classifier has been found to be a particularly suitable structure since only one sub-classifier is active at time, the others being switched off. Results from industrial applications show that the suggested design methodology provide an accuracy comparable with more traditional classifiers yet yielding a significant complexity and execution time reduction.
|Titolo:||Exploiting application locality to design fast, low power, low complexity neural classifiers|
|Settore Scientifico Disciplinare:||Settore INF/01 - Informatica|
Settore ING-INF/05 - Sistemi di Elaborazione delle Informazioni
|Data di pubblicazione:||mag-2005|
|Digital Object Identifier (DOI):||10.1109/ISCAS.2005.1465792|
|Tipologia:||Book Part (author)|
|Appare nelle tipologie:||03 - Contributo in volume|