This paper presents the characterization of an input/output interface circuit designed for multi-purpose pattern recognition applications compatible with low-voltage fully differential signaling (LVDS) standard. The driver and receiver circuits described in this work has been designed and fabricated in a 28 nm CMOS technology. The prototype chip has been mounted on a printed circuit board with physical characteristics similar to the real application case and fully validated up to 1 Gb/s with input random patterns.
Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition / G. Traversi, F. De Canio, V. Liberali, A. Stabile (IEEE INTERNATIONAL CONFERENCE ON CIRCUITS AND SYSTEMS). - In: 2018 IEEE International Symposium on Circuits and Systems (ISCAS)[s.l] : IEEE, 2018. - ISBN 9781538648810. - pp. 1-4 (( convegno ISCAS tenutosi a Firenze nel 2018.
Titolo: | Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition |
Autori: | |
Settore Scientifico Disciplinare: | Settore ING-INF/01 - Elettronica |
Data di pubblicazione: | 2018 |
Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/ISCAS.2018.8351576 |
Tipologia: | Book Part (author) |
Appare nelle tipologie: | 03 - Contributo in volume |
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