This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called "pattern". Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

AM06: The Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector / A. Annovi, M.M. Beretta, G. Calderini, F. Crescioli, L. Frontini, V. Liberali, S.R. Shojaii, A. Stabile. - In: JOURNAL OF INSTRUMENTATION. - ISSN 1748-0221. - 12(2017), pp. C04013.1-C04013.10. ((Intervento presentato al convegno Topical Workshop on Electronics for Particle Physics tenutosi a Karlsruhe nel 2016 [10.1088/1748-0221/12/04/C04013].

AM06: The Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

Frontini, L.;Liberali, V.;Shojaii, S. R.;Stabile, A.
2017

Abstract

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called "pattern". Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.
Digital electronic circuits; Trigger concepts and systems (hardware and software); VLSI circuits
Settore ING-INF/01 - Elettronica
Settore FIS/01 - Fisica Sperimentale
JOURNAL OF INSTRUMENTATION
Article (author)
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/2434/602684
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