This paper proposes a new model for the partitioning and scheduling of a specification on partially dynamically reconfigurable hardware. Although this problem can be solved optimally only by tackling its subproblems jointly, the exceeding complexity of such a task leads to a decomposition into two phases. The partitioning phase is based on a new graph-theoretic approach, which aims to obtain near optimality even if performed independently from the subsequent phase. For the scheduling phase, a new integer linear programming formulation and a heuristic approach are developed. Both take into account configuration prefetching and module reuse. The experimental results show that the proposed method compares favorably with existing solutions.
|Titolo:||Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs|
CORDONE, ROBERTO (Primo)
|Parole Chiave:||Field-programmable gate array (FPGA); Partitioning; Reconfigurable hardware (HW); Scheduling|
|Settore Scientifico Disciplinare:||Settore INF/01 - Informatica|
|Data di pubblicazione:||mag-2009|
|Digital Object Identifier (DOI):||10.1109/TCAD.2009.2015739|
|Appare nelle tipologie:||01 - Articolo su periodico|