We present a system architecture made of a motherboard with a Xilinx Zynq System on Chip (SoC) and a mezzanine board equipped with an Associative Memory chip (AM). The proposed architecture is designed to serve as an accelerator of general purpose algorithms based on pipeline processing and pattern recognition. We present the open source software and firmware developed to fully exploit the available communication channels between the ARM CPU and the FPGA using Direct Memory Access (DMA) technique and the AM using Multi-Gigabit Transceivers (MGT). We report the measured performances and discuss potential applications and future developments. The proposed architecture is compact, portable and provide a large communication bandwidth between components.
Heterogeneous computing system platform for high-performance pattern recognition applications / M.A. Mirzaei, V. Voisin, A. Annovi, G. Baulieu, M. Beretta, G. Calderini, S. Citraro, F. Crescioli, G. Galbit, V. Liberali, S.R. Shojaii, A. Stabile, W. Tromeu, S. Viret - In: 2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)[s.l] : IEEE, 2017 Jun 01. - ISBN 9781509043866. - pp. 1-4 (( Intervento presentato al 6. convegno MOCAST tenutosi a Thessaloniki nel 2017 [10.1109/MOCAST.2017.7937638].
Heterogeneous computing system platform for high-performance pattern recognition applications
V. Liberali;A. Stabile;
2017
Abstract
We present a system architecture made of a motherboard with a Xilinx Zynq System on Chip (SoC) and a mezzanine board equipped with an Associative Memory chip (AM). The proposed architecture is designed to serve as an accelerator of general purpose algorithms based on pipeline processing and pattern recognition. We present the open source software and firmware developed to fully exploit the available communication channels between the ARM CPU and the FPGA using Direct Memory Access (DMA) technique and the AM using Multi-Gigabit Transceivers (MGT). We report the measured performances and discuss potential applications and future developments. The proposed architecture is compact, portable and provide a large communication bandwidth between components.File | Dimensione | Formato | |
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