This paper presents an overview of the ATLAS Fast TracKer (FTK) processor, reporting the design of the system, its expected performance, and the current integration status. The FTK is an upgrade of the trigger system of the ATLAS experiment. The system is designed to reduce the event rate from the proton-proton collisions occurring at 40 MHz to about 1 kHz for the expected LHC luminosity (2 × 10^34 cm-^2s^-1). To achieve this selection rate, the FTK system must exploit an intensive use of particle tracking. To this purpose, a dedicated hardware tracker has been designed: the FTK processor. To achieve the required performance, FTK uses a combination of custom VLSI chips and latest generation FPGAs, all embedded in dedicated boards, and it exploits a fully parallel architecture. FTK provides track reconstruction based on the full silicon (inner) detector with resolution comparable to the offline reconstruction with a latency of approximately 100 μs.

FTK: A hardware real-time track finder for the ATLAS trigger system / A. Stabile - In: Modern Circuits and Systems Technologies (MOCAST), 2016 5th International Conference on[s.l] : IEEE, 2016 Jun 23. - ISBN 9781467396806. - pp. 1-4 (( Intervento presentato al 5. convegno Modern Circuits and Systems Technologies tenutosi a Thessaloniki nel 2016 [10.1109/MOCAST.2016.7495135].

FTK: A hardware real-time track finder for the ATLAS trigger system

A. Stabile
Primo
2016

Abstract

This paper presents an overview of the ATLAS Fast TracKer (FTK) processor, reporting the design of the system, its expected performance, and the current integration status. The FTK is an upgrade of the trigger system of the ATLAS experiment. The system is designed to reduce the event rate from the proton-proton collisions occurring at 40 MHz to about 1 kHz for the expected LHC luminosity (2 × 10^34 cm-^2s^-1). To achieve this selection rate, the FTK system must exploit an intensive use of particle tracking. To this purpose, a dedicated hardware tracker has been designed: the FTK processor. To achieve the required performance, FTK uses a combination of custom VLSI chips and latest generation FPGAs, all embedded in dedicated boards, and it exploits a fully parallel architecture. FTK provides track reconstruction based on the full silicon (inner) detector with resolution comparable to the offline reconstruction with a latency of approximately 100 μs.
FTK; Trigger; HEP; Parallel syste
Settore ING-INF/01 - Elettronica
23-giu-2016
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2434/512541
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