In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low logic value to trigger a high logic value of the single bit match line. A 18-input NOR gate performs this operation. The memory operation is triggered by the change of the least significant bit of the 18-bit input word, which is delayed w.r.t. The other bits. In this way, the logic does not require any clock. The proposed architecture is based on CMOS combinational logic, and it does not require any precharge operation, nor control and timing logic. The Associative Memory block is useful for several pattern recognition tasks, such as track recognition in high energy physics experiments, and image recognition for medical applications.
A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications / A. Annovi, A. Baschirotto, M.M. Beretta, N.V. Biesuz, S. Citraro, F. Crescioli, M. De Matteis, F. Fary, L. Frontini, P. Giannetti, V. Liberali, P. Luciano, F. Palla, A. Pezzotta, S.R. Shojaii, C. Sotiropoulou, A. Stabile - In: Electronics, Circuits, and Systems (ICECS), 2015 IEEE International Conference on[s.l] : IEEE, 2015 Dec. - ISBN 9781509002467. - pp. 392-395 (( convegno ICECS tenutosi a Cairo nel 2015.
A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications
L. Frontini;V. Liberali;A. Stabile
2015
Abstract
In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low logic value to trigger a high logic value of the single bit match line. A 18-input NOR gate performs this operation. The memory operation is triggered by the change of the least significant bit of the 18-bit input word, which is delayed w.r.t. The other bits. In this way, the logic does not require any clock. The proposed architecture is based on CMOS combinational logic, and it does not require any precharge operation, nor control and timing logic. The Associative Memory block is useful for several pattern recognition tasks, such as track recognition in high energy physics experiments, and image recognition for medical applications.File | Dimensione | Formato | |
---|---|---|---|
icecs2015_1.pdf
accesso riservato
Tipologia:
Publisher's version/PDF
Dimensione
218.31 kB
Formato
Adobe PDF
|
218.31 kB | Adobe PDF | Visualizza/Apri Richiedi una copia |
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.