In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low logic value to trigger a high logic value of the single bit match line. A 18-input NOR gate performs this operation. The memory operation is triggered by the change of the least significant bit of the 18-bit input word, which is delayed w.r.t. The other bits. In this way, the logic does not require any clock. The proposed architecture is based on CMOS combinational logic, and it does not require any precharge operation, nor control and timing logic. The Associative Memory block is useful for several pattern recognition tasks, such as track recognition in high energy physics experiments, and image recognition for medical applications.
|Titolo:||A XOR-based associative memory block in 28 nm CMOS for interdisciplinary applications|
|Parole Chiave:||Electrical and Electronic Engineering|
|Settore Scientifico Disciplinare:||Settore ING-INF/01 - Elettronica|
|Data di pubblicazione:||dic-2015|
|Digital Object Identifier (DOI):||http://dx.doi.org/10.1109/ICECS.2015.7440331|
|Tipologia:||Book Part (author)|
|Appare nelle tipologie:||03 - Contributo in volume|