Improvement of radiation tolerance in CMOS ICs through layout-oriented simulation

This paper proposes a methodology to design radiation-hardened ICs, suitable for space applications and high-energy physics experiments. The miniaturization of ICs has brought an increase of circuit logic errors due to radiation, also at ground level. The increased complexity of IC design due to technology scaling requires new tools to design rad-hard circuits. In this paper, we propose a design tool that employs a layout-oriented simulation approach to identify the sensitive IC area and provide data about the effects due to radiation. The simulation tool is implemented in Cadence LayoutGXL. The proposed approach will help to have a more efficient IC design reducing design time and costs related to the need of fabricating prototypes to be characterized under radiation to test their hardness.