The dynamic clocked comparator using a parametric amplifier is proposed and designed using a concept of the charge transfer amplification (CTA). A low gain (5 V/V) reverse discrete-time parametric amplifier (RDTPA) was used as a pre-amplifier stage of the proposed comparator. The level shifter scheme to nullify an input common-mode voltage (VCMI) shows minimal deviation for varying process corners. The complete design including the latch and the RDTPA is designed and fabricated in an STMicroelectronics 32 nm CMOS technology with the supply voltage of 1 V and a sampling frequency of 50 MHz. The fabricated chip results show 7 mV of an input offset voltage, 120 μW of power consumption and 2.4 pJ of energy per comparison.
Parametric amplifier based dynamic clocked comparator / H. Shrimali, V. Liberali. - In: SOLID-STATE ELECTRONICS. - ISSN 0038-1101. - 101(2014 Nov), pp. 85-89. ((Intervento presentato al convegno International semiconductor device research symposium (ISDRS) tenutosi a Bethesda (Maryland) nel 2013 [10.1016/j.sse.2014.06.043].
Parametric amplifier based dynamic clocked comparator
H. ShrimaliPrimo
;V. LiberaliUltimo
2014
Abstract
The dynamic clocked comparator using a parametric amplifier is proposed and designed using a concept of the charge transfer amplification (CTA). A low gain (5 V/V) reverse discrete-time parametric amplifier (RDTPA) was used as a pre-amplifier stage of the proposed comparator. The level shifter scheme to nullify an input common-mode voltage (VCMI) shows minimal deviation for varying process corners. The complete design including the latch and the RDTPA is designed and fabricated in an STMicroelectronics 32 nm CMOS technology with the supply voltage of 1 V and a sampling frequency of 50 MHz. The fabricated chip results show 7 mV of an input offset voltage, 120 μW of power consumption and 2.4 pJ of energy per comparison.
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