SRAM-based Field Programmable Gate Arrays (SRAM-FPGA) are more and more employed in today's applications. In space and avionic applications their operations might be harmed by occurrence of radiation-induced upsets, or Single Event Upsets (SEU), which require the adoption of mitigation techniques. In these devices the majority of the configuration memory rules the interconnection setting. In devices employing “switch matrix” routing, the density of interconnections in switch arrays seems to be a critical point. The higher the interconnection density (i.e., the higher the number of interconnection segments activated by the same switch matrix), the higher the probability of an upset due to a configuration bit controlling the switch matrix. This paper presents an approach to estimate the SEU sensitivity of programmable interconnections of SRAM-based FPGAs as a function of the density of programmable interconnection points inside device configurable logic blocks. A probabilistic model of the SEU effects in programmable interconnection points of Xilinx SRAM-FPGAs is described. The application of the proposed approach to a set of sample designs is illustrated.

A preliminary study about SEU effects on programmable interconnections of SRAM-based FPGAs / M. Alderighi, F. Casini, S. D'Angelo, A. Gravina, V. Liberali, M. Mancini, P. Musazzi, S. Pastore, M. Sassi, G. Sorrenti. - In: JOURNAL OF ELECTRONIC TESTING. - ISSN 0923-8174. - 29:3(2013 Jun), pp. 341-350.

A preliminary study about SEU effects on programmable interconnections of SRAM-based FPGAs

V. Liberali;
2013-06

Abstract

SRAM-based Field Programmable Gate Arrays (SRAM-FPGA) are more and more employed in today's applications. In space and avionic applications their operations might be harmed by occurrence of radiation-induced upsets, or Single Event Upsets (SEU), which require the adoption of mitigation techniques. In these devices the majority of the configuration memory rules the interconnection setting. In devices employing “switch matrix” routing, the density of interconnections in switch arrays seems to be a critical point. The higher the interconnection density (i.e., the higher the number of interconnection segments activated by the same switch matrix), the higher the probability of an upset due to a configuration bit controlling the switch matrix. This paper presents an approach to estimate the SEU sensitivity of programmable interconnections of SRAM-based FPGAs as a function of the density of programmable interconnection points inside device configurable logic blocks. A probabilistic model of the SEU effects in programmable interconnection points of Xilinx SRAM-FPGAs is described. The application of the proposed approach to a set of sample designs is illustrated.
field programmable gate array ; single event upsets ; dependability evaluation ; probabilistic models ; XDL
Settore ING-INF/01 - Elettronica
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/2434/222304
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