Temporal and spatial locality of the inputs, i.e., the property allowing a classifier to receive the same samples over time - or samples belonging to a neighborhood - with high probability, can be translated into the design of embedded classifiers. The outcome is a computational complexity and power aware design particularly suitable for implementation. A classifier based on the gated-parallel family has been found particularly suitable for exploiting locality properties: Subclassifiers are generally small, independent each other, and controlled by a master-enabling module granting that only a subclassifier is active at a time, the others being switched off. By exploiting locality properties we obtain classifiers with accuracy comparable with the ones designed without integrating locality but gaining a significant reduction in computational complexity and power consumption.

Exploiting application locality to design low-complexity, highly performing, and power-aware embedded classifiers / C. Alippi, F. Scotti. - In: IEEE TRANSACTIONS ON NEURAL NETWORKS. - ISSN 1045-9227. - 17:3(2006 May), pp. 745-754.

Exploiting application locality to design low-complexity, highly performing, and power-aware embedded classifiers

F. Scotti
Ultimo
2006

Abstract

Temporal and spatial locality of the inputs, i.e., the property allowing a classifier to receive the same samples over time - or samples belonging to a neighborhood - with high probability, can be translated into the design of embedded classifiers. The outcome is a computational complexity and power aware design particularly suitable for implementation. A classifier based on the gated-parallel family has been found particularly suitable for exploiting locality properties: Subclassifiers are generally small, independent each other, and controlled by a master-enabling module granting that only a subclassifier is active at a time, the others being switched off. By exploiting locality properties we obtain classifiers with accuracy comparable with the ones designed without integrating locality but gaining a significant reduction in computational complexity and power consumption.
applicational-level design; classifier design; embedded systems; gated-parallel classifiers; power-aware design
Settore INF/01 - Informatica
Settore ING-INF/05 - Sistemi di Elaborazione delle Informazioni
mag-2006
Article (author)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2434/22214
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