In the design of the Silicon Vertex Tracker for the high luminosity SuperB collider, very challenging requirements are set by physics and background conditions on its innermost Layer0: small radius (about 1.5 cm), resolution of 10215 mm in both coordinates, low material budget < 1% X0, and the ability to withstand a background hit rate of several tens of MHz/cm^2. Thanks to an intense R&D program the development of Deep NWell CMOS MAPS (with the ST Microelectronics 130 nm process) has reached a good level of maturity and allowed for the first time the implementation of thin CMOS sensors with similar functionalities as in hybrid pixels, such as pixel-level sparsification and fast time stamping. Further MAPS performance improvements are currently under investigation with two different approaches: the INMAPS CMOS process, featuring a quadruple well and a high resistivity substrate, and 3D CMOS MAPS, realized with vertical integration technology. In both cases specific features of the processes chosen can improve charge collection efficiency, with respect to a standard DNW MAPS design, and allow to implement a more complex in-pixel logic in order to develop a faster readout architecture. Prototypes of MAPS matrix, suitable for application in the SuperB Layer0, have been realized with the INMAPS 180 nm process and the 130 nm Chartered/Tezzaron 3D process and results of their characterization will be presented in this paper.
|Titolo:||Recent developments on CMOS MAPS for the superB silicon vertex tracker|
|Parole Chiave:||solid state detectors ; vertex detectors ; CMOS MAPS pixel sensors ; hybrid pixels ; charged particle tracking|
|Settore Scientifico Disciplinare:||Settore FIS/01 - Fisica Sperimentale|
Settore ING-INF/01 - Elettronica
|Data di pubblicazione:||ago-2013|
|Digital Object Identifier (DOI):||10.1016/j.nima.2012.10.084|
|Appare nelle tipologie:||01 - Articolo su periodico|