The asymmetric e+ e- collider SuperB is designed to deliver a high luminosity, greater than 10^36 cm^-2 s^-1 , with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%.

The front-end chip of the SuperB SVT detector / F. Giorgi, D. Comotti, M. Manghisoni, V. Re, G. Traversi, L. Fabbri, A. Gabrielli, G. Pellegrini, C. Sbarra, N. Semprini Cesari, S. Valentinetti, M. Villa, A. Zoccoli, A. Berra, D. Lietti, M. Prest, A. Bevan, F. Wilson, G. Beck, J. Morris, F. Gannaway, R. Cenci, L. Bombelli, M. Citterio, S. Coelli, C. Fiorini, V. Liberali, M. Monti, B. Nasri, N. Neri, F. Palombo, A. Stabile, G. Balestri, G. Batignani, A. Bernardelli, S. Bettarini, F. Bosi, G. Casarosa, M. Ceccanti, F. Forti, M.A. Giorgi, A. Lusiani, P. Mammini, F. Morsani, B. Oberhof, E. Paoloni, A. Perez, G. Petragnani, A. Profeti, G. Rizzo, A. Soldani, J. Walsh, L. Gaioni, A. Manazza, E. Quartieri, L. Ratti, S. Zucca, G.F. Dalla Betta, G. Fontana, L. Pancheri, M. Povoli, G. Verzellesi, L. Bosisio, L. Lanceri, I. Rashevskaya, C. Stella, L. Vitale. - In: NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH. SECTION A, ACCELERATORS, SPECTROMETERS, DETECTORS AND ASSOCIATED EQUIPMENT. - ISSN 0168-9002. - 718(2013 Aug), pp. 180-183. ((Intervento presentato al 12. convegno Pisa Meeting on Advanced Detectors tenutosi a Pisa nel 2012.

The front-end chip of the SuperB SVT detector

V. Liberali;N. Neri;F. Palombo;A. Stabile;
2013

Abstract

The asymmetric e+ e- collider SuperB is designed to deliver a high luminosity, greater than 10^36 cm^-2 s^-1 , with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%.
HEP; Tracker; Front end; Strip; Fast readout; ASIC; VLSI
Settore FIS/01 - Fisica Sperimentale
Settore ING-INF/01 - Elettronica
ago-2013
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2434/221477
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