In this paper we describe a Content Addressable Memory (CAM) architecture based on a new custom cell, called XORAM. The cell is composed by two main blocks: a 6T-SRAM, and a 4T-XOR logic gate. Each XORAM cell compares the input data on the bit line with the data stored in the 6T-SRAM cell. The output matching bit is obtained by performing a NOR operation between all bits of the XORAM cells storing the word. The proposed architecture is based on a fully-CMOS combinational logic, and it does nor require any precharge operation or control and timing logic. A compact full-custom layout has been designed for a memory organized in 18-bit words, to reduce both area and power consumption. Compared with a conventional selective precharge match-line technique, the proposed circuit occupies less area. Simulation results demonstrate that power consumption is reduced by a factor of 8.
|Titolo:||A new XOR-based Content Addressable Memory architecture|
|Autori interni:||SHOJAII, SEYEDRUHOLLAH (Secondo)|
STABILE, ALBERTO (Penultimo)
LIBERALI, VALENTINO (Ultimo)
|Parole Chiave:||associative memory ; content-addressable memory (CAM) ; hardware lookup ; low power|
|Settore Scientifico Disciplinare:||Settore ING-INF/01 - Elettronica|
|Data di pubblicazione:||dic-2012|
|Enti collegati al convegno:||IEEE|
|Digital Object Identifier (DOI):||10.1109/ICECS.2012.6463629|
|Tipologia:||Book Part (author)|
|Appare nelle tipologie:||03 - Contributo in volume|
- PubMed Central loading...