This paper presents a low-cost approach to concurrent error detection in a high-performance CORDIC processor based on a conditional-sum scheme. The specific characteristics of the CORDIC computation and the processor allow fault detection at a low increase in circuit complexity and latency. The detection scheme is based on use of the AN codes for the arithmetic part and on duplication of the rotation direction generators. Granular-pipelining has been applied to provide a variety of different performance tradeoffs, all with the same fault detection capabilities.
Fault-tolerant high-performance CORDIC processors / J. Kwak, V. Piuri, E.E. Swartzlander - In: Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems[s.l] : IEEE Computer Society, 2000. - ISBN 0769507190. - pp. 164-172
Fault-tolerant high-performance CORDIC processors
V. PiuriSecondo
;
2000
Abstract
This paper presents a low-cost approach to concurrent error detection in a high-performance CORDIC processor based on a conditional-sum scheme. The specific characteristics of the CORDIC computation and the processor allow fault detection at a low increase in circuit complexity and latency. The detection scheme is based on use of the AN codes for the arithmetic part and on duplication of the rotation direction generators. Granular-pipelining has been applied to provide a variety of different performance tradeoffs, all with the same fault detection capabilities.
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