This paper presents a low-cost approach to concurrent error correction in high-performance CORDIC processors by using time-shared triple modular redundancy. Operands are partitioned into three sets of disjoint digits and operations are performed three times on different hardware components to correct possible errors by majority voting. The approach has limited latency increase and throughput reduction. Pipelining can be used to maintain the same throughput as a conventional design.
Time-shared TMR for fault-tolerant CORDIC processors / J.H. Kwak, V. Piuri, E. Swartzander - In: 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221)[s.l] : IEEE, 2001. - ISBN 0-7803-7041-4. - pp. 1241-1244 [10.1109/ICASSP.2001.941149]
Time-shared TMR for fault-tolerant CORDIC processors
V. PiuriSecondo
;
2001
Abstract
This paper presents a low-cost approach to concurrent error correction in high-performance CORDIC processors by using time-shared triple modular redundancy. Operands are partitioned into three sets of disjoint digits and operations are performed three times on different hardware components to correct possible errors by majority voting. The approach has limited latency increase and throughput reduction. Pipelining can be used to maintain the same throughput as a conventional design.
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
