We propose a new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new associative memory project: it maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.
Associative memory design for the fast track processor (FTK) at ATLAS / A. Annovi, R. Beccherle, M. Beretta, E. Bossini, F. Crescioli, M. Dell'Orso, P. Giannetti, J. Hoff, T. Liu, V. Liberali, I. Sacco, A. Schoening, H.K. Soltveit, A. Stabile, R. Tripiccione, G. Volpi (IEEE CONFERENCE RECORD - NUCLEAR SCIENCE SYMPOSIUM & MEDICAL IMAGING CONFERENCE). - In: 2011 IEEE Nuclear Science Symposium Conference RecordPiscataway : IEEE, 2012. - ISBN 9781467301183. - pp. 141-146 (( convegno Nuclear science symposium and medical imaging conference : NSS/MIC tenutosi a Valencia nel 2011 [10.1109/NSSMIC.2011.6154467].
Associative memory design for the fast track processor (FTK) at ATLAS
V. Liberali;A. Stabile;
2012
Abstract
We propose a new generation of VLSI processors for pattern recognition, based on associative memory architecture, optimized for online track finding in high-energy physics experiments. We describe the architecture, the technology studies and the prototype design of a new associative memory project: it maximizes the pattern density on the ASIC, minimizes the power consumption and improves the functionality for the fast tracker processor proposed to upgrade the ATLAS trigger at LHC.
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