Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior.
Extracting exact time bounds from logical proofs / M. Ferrari, C. Fiorentini, M. Ornaghi - In: Logic based program synthesis and transformation : 11th international workshop, LOPSTR 2001, Paphos, Cyprus, november 28-30, 2001 : selected papers / [a cura di] A. Pettorossi. - Berlin : Springer, 2002. - ISBN 9783540439158. - pp. 245-267 (( Intervento presentato al 11. convegno International Workshop on Logic-based Program Synthesis and Transformation tenutosi a Paphos, Cyprus nel 2001 [10.1007/3-540-45607-4_14].
Extracting exact time bounds from logical proofs
C. Fiorentini;M. Ornaghi
2002
Abstract
Accurate evaluation of delays of combinatorial circuits is crucial in circuit verification and design. In this paper we present a logical approach to timing analysis which allows us to compute exact stabilization bounds while proving the correctness of the boolean behavior.
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