Efficient implementation of neural networks requires high-performance architectures, while VLSI realization for mission-critical applications must include fault tolerance. Contemporaneous solution of such problems has not yet been completely afforded in the literature. This paper focuses both on data representation to support high-performance neural computation and on error detection to provide the basic information for fault tolerance by using the redundant binary representation with a three-rail logic implementation. Costs and performances are evaluated referring to multilayered feed-forward networks.
|Titolo:||High performance fault-tolerant digital neural networks|
PIURI, VINCENZO (Ultimo)
|Parole Chiave:||Concurrent error detection; High-performance architecture; Neural architecture; Redundant binary representation; Three-rail logic; Unidirectional errors|
|Settore Scientifico Disciplinare:||Settore ING-INF/05 - Sistemi di Elaborazione delle Informazioni|
|Data di pubblicazione:||1998|
|Digital Object Identifier (DOI):||10.1109/12.660173|
|Appare nelle tipologie:||01 - Articolo su periodico|