A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder. Such schemes offer a considerable savings of components while preserving high throughput. These schemes can be generalized by using (p, q) parallel counters to obtain pipelined adders for more than two numbers.
Pipelined adders / L. Dadda, V. Piuri. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - 45:3(1996), pp. 348-356.
Pipelined adders
V. PiuriUltimo
1996
Abstract
A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder. Such schemes offer a considerable savings of components while preserving high throughput. These schemes can be generalized by using (p, q) parallel counters to obtain pipelined adders for more than two numbers.
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