An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16- bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. An experimental study is carried out to determine the best set of parameters for on-line execution. It is observed that small population size leads to more effective results when short execution time is required. An application of the evolutionary approach presented in the paper for on-line tuning of the function during cache memory operation is also discussed.
On-line evolution of FPGA-based circuits : a case study on hash functions / E. Damiani, A.G.B. Tettamanzi, V. Liberali - In: Proceedings of the first NASA/DoD workshop on evolvable hardware : Pasadena, California, july 19-21, 1999 / [a cura di] A. Stoica. - Los Alamitos : Institute of electrical and electronics engineers, 1999. - ISBN 0769502563. - pp. 26-33 (( Intervento presentato al 1. convegno NASA/DoD Workshop on Evolvable Hardware tenutosi a Pasadena nel 1999 [10.1109/EH.1999.785432].
On-line evolution of FPGA-based circuits : a case study on hash functions
E. DamianiPrimo
;A.G.B. TettamanziSecondo
;V. LiberaliUltimo
1999
Abstract
An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16- bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. An experimental study is carried out to determine the best set of parameters for on-line execution. It is observed that small population size leads to more effective results when short execution time is required. An application of the evolutionary approach presented in the paper for on-line tuning of the function during cache memory operation is also discussed.
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