In this paper a FPGA implementation of a novel neural stochastic model for solving constrained NP-hard problems is proposed and developed. The hardware implementation allows to obtain high computation speed by exploiting parallelism, as the neuron update and the constraint violation check phases can be performed simultaneously. The neural system has been tested on random and benchmark graphs, showing good performance with respect to the same heuristic for the same problems. Furthermore, the computational speed of the FPGA implementation has been measured and compared to software implementation. The developed architecture features dramatically faster computations with respect to the software implementation, even adopting a low-cost FPGA chip
FPGA Implementation of an Adaptive Stochastic Neural Model / G. Grossi, F. Pedersini (LECTURE NOTES IN COMPUTER SCIENCE). - In: Artificial Neural Networks / [a cura di] J.Marques de Sá, L. A. Alexandre, W. Duch, D. P. Mandic. - Berlin : Springer, 2007. - ISBN 9783540746898. - pp. 559-568 (( Intervento presentato al 17. convegno ICANN International Conference on Artificial Neural Networks September, 9th - 13th tenutosi a Porto (Portugal) nel 2007 [10.1007/978-3-540-74690-4_57].
FPGA Implementation of an Adaptive Stochastic Neural Model
G. GrossiPrimo
;F. PedersiniUltimo
2007
Abstract
In this paper a FPGA implementation of a novel neural stochastic model for solving constrained NP-hard problems is proposed and developed. The hardware implementation allows to obtain high computation speed by exploiting parallelism, as the neuron update and the constraint violation check phases can be performed simultaneously. The neural system has been tested on random and benchmark graphs, showing good performance with respect to the same heuristic for the same problems. Furthermore, the computational speed of the FPGA implementation has been measured and compared to software implementation. The developed architecture features dramatically faster computations with respect to the software implementation, even adopting a low-cost FPGA chipPubblicazioni consigliate
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