In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most important and challenging tasks. In this framework, the use of both voltage scaling and body biasing techniques is a mainstream strategy largely used for leakage power reduction. This work presents a case study to evaluate the impact of these techniques on an industrial microprocessor-based design. We analyze the impact of body biasing in terms of area penalties and routing efforts. Furthermore, a complete analysis flow is proposed to evaluate the achievable leakage reduction and the expected performance degradation. In order to overcome the limited spectrum of operating configurations covered by a given library set, we propose a practical and effective methodology based on a standard digital design and characterization flow. By using this procedure, a designer can efficiently evaluate the most appropriate leakage/timing trade-offs, and consequently determine the best supply voltage and biasing configurations to implement the design. The experimental results on our testcase demonstrate that body biasing leads to a leakage reduction up to six times with respect to the standard reference supply voltage configuration.

Exploiting body biasing for leakage reduction : a case study / A. Manuzzato, F. Campi, D. Rossi, V. Liberali, D. Pandini - In: 2013 IEEE Computer Society annual symposium on VLSI (ISVLSI) : emerging VLSI technologies and architectures : Natal, Brazil, August 5-7, 2013 / [a cura di] F. Kastensmidt, R. Reis, L. Soares Indrusiak, G. Sassatelli, M. Rutzig. - [s.l] : IEEE, 2013 Aug. - ISBN 978-1-4799-1331-2. - pp. 133-138 (( convegno Computer Society annual symposium on VLSI (ISVLSI) tenutosi a Natal, Brasil nel 2013 [10.1109/ISVLSI.2013.6654635].

Exploiting body biasing for leakage reduction : a case study

A. Manuzzato;V. Liberali
Penultimo
;
2013

Abstract

In modern System-on-Chip (SoC) designs, the fulfillment of power constraints is one of the most important and challenging tasks. In this framework, the use of both voltage scaling and body biasing techniques is a mainstream strategy largely used for leakage power reduction. This work presents a case study to evaluate the impact of these techniques on an industrial microprocessor-based design. We analyze the impact of body biasing in terms of area penalties and routing efforts. Furthermore, a complete analysis flow is proposed to evaluate the achievable leakage reduction and the expected performance degradation. In order to overcome the limited spectrum of operating configurations covered by a given library set, we propose a practical and effective methodology based on a standard digital design and characterization flow. By using this procedure, a designer can efficiently evaluate the most appropriate leakage/timing trade-offs, and consequently determine the best supply voltage and biasing configurations to implement the design. The experimental results on our testcase demonstrate that body biasing leads to a leakage reduction up to six times with respect to the standard reference supply voltage configuration.
body biasing ; leakage reduction ; voltage scaling ; power dissipation ; low power ; timing analysis
Settore ING-INF/01 - Elettronica
ago-2013
IEEE
Book Part (author)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/2434/228851
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