In this paper we describe a Content Addressable Memory (CAM) architecture based on a new custom cell, called XORAM. The cell is composed by two main blocks: a 6T-SRAM, and a 4T-XOR logic gate. Each XORAM cell compares the input data on the bit line with the data stored in the 6T-SRAM cell. The output matching bit is obtained by performing a NOR operation between all bits of the XORAM cells storing the word. The proposed architecture is based on a fully-CMOS combinational logic, and it does nor require any precharge operation or control and timing logic. A compact full-custom layout has been designed for a memory organized in 18-bit words, to reduce both area and power consumption. Compared with a conventional selective precharge match-line technique, the proposed circuit occupies less area. Simulation results demonstrate that power consumption is reduced by a factor of 8.
A new XOR-based Content Addressable Memory architecture / L. Frontini, S. Shojaii, A. Stabile, V. Liberali - In: 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)[s.l] : IEEE, 2012 Dec. - ISBN 9781467312592. - pp. 701-704 (( Intervento presentato al 19. convegno International Conference on Electronics, Circuits, and Systems tenutosi a Sevilla nel 2012 [10.1109/ICECS.2012.6463629].
A new XOR-based Content Addressable Memory architecture
L. Frontini;S. ShojaiiSecondo
;A. StabilePenultimo
;V. LiberaliUltimo
2012
Abstract
In this paper we describe a Content Addressable Memory (CAM) architecture based on a new custom cell, called XORAM. The cell is composed by two main blocks: a 6T-SRAM, and a 4T-XOR logic gate. Each XORAM cell compares the input data on the bit line with the data stored in the 6T-SRAM cell. The output matching bit is obtained by performing a NOR operation between all bits of the XORAM cells storing the word. The proposed architecture is based on a fully-CMOS combinational logic, and it does nor require any precharge operation or control and timing logic. A compact full-custom layout has been designed for a memory organized in 18-bit words, to reduce both area and power consumption. Compared with a conventional selective precharge match-line technique, the proposed circuit occupies less area. Simulation results demonstrate that power consumption is reduced by a factor of 8.File | Dimensione | Formato | |
---|---|---|---|
2012-A_new_XOR-based_Content_Addressable_Memory_architecture.pdf
accesso riservato
Tipologia:
Publisher's version/PDF
Dimensione
1.05 MB
Formato
Adobe PDF
|
1.05 MB | Adobe PDF | Visualizza/Apri Richiedi una copia |
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.