A 'combination of multiple classifier' design for low-complex, highly performing and power-aware classifiers

In this paper we study the relationships among the Combination of Multiple Classifier design philosophy, application level properties such as temporal and spatial locality of the inputs and low level aspects immediately impacting on power consumption, cache miss and computational complexity reduction. The CMC structure requires a set of independent simple sub-classifiers, each of which ruling in an application sub-domain under the control of a master enabling module and is particularly appealing in embedded system implementation. Only a sub-classifier is active at a time, the others being switched off.