Efficient implementation of neural networks requires high-performance architectures, while VLSI realization for mission-critical applications must include fault tolerance. Contemporaneous solution of such problems has not yet been completely afforded in the literature. This paper focuses both on data representation to support high-performance neural computation and on error detection to provide the basic information for fault tolerance by using the redundant binary representation with a three-rail logic implementation. Costs and performances are evaluated referring to multilayered feed-forward networks.
High performance fault-tolerant digital neural networks / S. Bettola, V. Piuri. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - 47:3(1998), pp. 357-363.
High performance fault-tolerant digital neural networks
V. PiuriUltimo
1998
Abstract
Efficient implementation of neural networks requires high-performance architectures, while VLSI realization for mission-critical applications must include fault tolerance. Contemporaneous solution of such problems has not yet been completely afforded in the literature. This paper focuses both on data representation to support high-performance neural computation and on error detection to provide the basic information for fault tolerance by using the redundant binary representation with a three-rail logic implementation. Costs and performances are evaluated referring to multilayered feed-forward networks.Pubblicazioni consigliate
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